Modern semiconductor devices, such as integrated circuits, are typically fabricated from wafers of semiconductor material. The wafers are fabricated by a succession of patterned layers of semiconductor material. Circuit patterns are fabricated using a variety of long established techniques, for example, lithographic techniques. Precise positioning and alignment during fabrication is important in manufacturing accurate patterns. For example, alignment control of the stepper tool is important in ensuring a consistent process. Statistical stepper alignment methodologies are established, in which statistical techniques are used to determine the alignment of a reticle with a pattern created by or in association with the stepper to facilitate alignment of the stepper. The technique typically uses images generated within the stepper optics, or projected onto the wafer by the stepper optics. Similar statistical methods have been employed to align for example an exposure tool during pattern fabrication.
Although such alignment technology has performed well, and is important in device fabrication, it relates to alignment of fabrication tooling only. This can be a limitation with semiconductor structures having a succession of pattern layers of semiconductor material, where it is desirable to be able to determine the misregistration between fabricated layers themselves.
Overlay metrology in semiconductor device fabrication is used to determine how well one printed layer is overlaid on a previously printed layer. Close alignment of each layer at all points within the device is important for reaching the design goals and hence the required quality and performance of the manufactured device. It is consequently important for the efficiency of the manufacturing process that any alignment error between two patterned layers on a wafer can be measured quickly and accurately. It is similarly important to be able to measure any alignment error between successive exposures in the same layer. Discussion here of two layers applies as well to two exposures in the same layer.
Misregistration between layers is referred to as overlay error. Overlay metrology tools are used to measure the overlay error. This information may be fed into a closed loop system to correct the overlay error.
Current overlay metrology uses optically readable target marks or patterns printed onto layers of a semiconductor wafer during fabrication. The relative displacement of two successive layers is measured by imaging the patterns at high magnification, digitizing the images, and processing the image data using various known image analysis algorithms to quantify the overlay error. Overlay metrology techniques thus involve the direct measurement of misregistration between patterns provided in direct association with each of the layers. In particular, target marks or patterns are developed in or on the surface of each of the layers, rather than being latent images, or images generated within or projected from the optics of an imaging instrument.
The pattern of the target mark may be applied to the wafer by any suitable method. The mark is often preferably printed onto the wafer layers, for example using photolithographic methods. Typically, the same technique is used to apply overlay target marks on each of two or more wafer layers to be tested to enable alignment information representative of the alignment of the layers to be measured. Accuracy of layer alignment should correspond to accuracy of circuit pattern alignment within the fabricated wafer.
Current overlay metrology is normally practiced by printing targets with rectangular symmetry. For each measurement, two targets are printed, one in the current layer and one in a previous layer, or one in association with each pattern in a common layer. The choice of which previous layer to use is determined by process tolerances. The two targets usually have a nominally common center, but are printed with different sizes so that they can be differentiated. Normally, but not always, the target printed in the current layer is the smaller of the two targets. An overlay measurement in such a system is the actual measured displacement of the centers of the two targets.
The size of the targets is currently often designed so that both targets can be imaged simultaneously by a bright-field microscope. Due to imaging considerations, the larger of the two targets is typically about 25 μm square on the outside. This arrangement permits capture of all of the necessary data for the performance of the measurement from a single image. Measurements at a rate of one in every second or less are possible using current technology.
This procedure generally requires that the target and the target image be symmetric, since otherwise there is no uniquely defined center point. Without symmetry, there is an uncertainty in the measurement, which may be more than can be tolerated. Preferred sizes and shapes of current designs of targets to be measured are generally well known. The targets are positioned in the scribe area at the edge of the fabricated circuit.
It is generally highly desirable that the measurement targets maintain axial symmetry about the optical axis of the measurement tool, since accurate measurement requires very close control of image aberrations. In current practice, this can only be achieved for images at or centered about the system axis. In most known systems, measurements are therefore made from the targets by computing a center line for each different target. The overlay measurement is the difference in the center lines. Most of the target designs in general use permit measurement of the vertical and horizontal overlay displacement from a single image.
Measurement errors must be controlled to a very small amount. These errors can be classified as random errors, characterized by determination of measurement precision; and systematic errors, characterized by tool induced errors, tool-to-tool measurement differences and errors introduced by asymmetry in the targets being measured. Successful application of overlay metrology to semiconductor process control generally requires that these errors (combined) be less than 10% of the process control budget. The process control budget is approximately one third of the smallest dimension patterned by the process. The smallest feature sizes being printed in semiconductor device manufacture is currently 65 nm. These features will become progressively even smaller. The overlay measurement error budget is therefore now 3 nm or less, and will become yet smaller in the foreseeable future.
Measurement precision is easily determined by analysis of the variations of repeated measurements. Different forms of precision may be determined by well known appropriate methods, allowing determination of the static, short-term and long-term components of precision.
Determining the contribution of the measurement tool alone to errors is achieved by comparing measurements made with the target in its normal presentation, with a measurement made after rotating the target by 180° with respect to the imaging system. Ideally the measurement will simply change sign. The average of the measurements at 0° and 180° is called Tool Induced Shift (TIS), as is well known to those skilled in the art. TIS is widely accepted as a measure of the tool's systematic error contribution. Measurements of TIS differ from tool to tool and with process layer Subtraction of the estimated TIS error from the measurements allows removal of the TIS error from the measurements, but at the expense of the additional time taken to measure the target twice.
Different tools, even when of the same type, will make slightly different measurements, even after allowing for precision and TIS errors. The magnitude of this error can be determined experimentally by comparing the averages of repeated measurements at 0° and 180° on two or more tools.
The contributions of precision, TIS variation and tool-to-tool differences are normally combined through a root-sum-square product, or alternative appropriate method, to determine the total measurement uncertainty due to the measurement process. The total measurement uncertainty should be less than 10% of the overall overlay budget for the process if the metrology is to have value. Existing measurement tools and procedures achieve a total uncertainty sufficient for current manufacturing techniques but insufficient for the future requirements of smaller feature sizes.
Overlay metrology today is performed almost exclusively by bright-field microscopy. Patterns are fabricated at the edge of the imaged field, in the scribe-line area of the device, specifically for the purpose of metrology. Currently, some device features are smaller than the wavelength of visible light. As a result, the targets generally are significantly larger than these very small features (approximately 25 μm outside dimensions are normal as shown in FIG. 1). The current standard target is large so that the elements are effectively isolated.
There are three sources of error to be considered. The first source of error is imperfection in the manufacture of the target which leads to an uncertainty in its location. An example of this is physical asymmetry of the target, caused perhaps by uneven deposition of a metal film. A second source of error is the difference in the displacement of the two layers at the measurement target and the genuine overlay of the same layers in the device being manufactured. These can arise from errors in the design and manufacture of the reticles used to create the patterns on the wafer, proximity effects in the printing process and distortion of the films after printing by other process steps. A third source of error is shift in the apparent relative position of the two layers due to proximity effects when the measured image is formed. These measurement errors represent a practical limitation of the current state of the art and can cause serious problems in the application of overlay metrology to semiconductor process control.
Error from imperfection in manufacture of the target can sometimes be reduced by fabricating the features in the measured targets from much smaller objects, such as lines or holes. These smaller features are printed at the design rule for the process, currently in the range 0.1-0.2 μm, and are grouped close together. They are too small to be individually resolved by optical microscopes used in overlay metrology tools. The small features are grouped into larger shapes in the pattern of traditional overlay targets. The use of small features avoids some of the mechanisms causing imperfections in the shape of the manufactured targets, in part by taking advantage of the optimization of the manufacturing process for objects of this size and shape.
If the various parts of the measurement target are brought too close together then they will interact during formation of the image in the measurement tool (R Silver et al, SPIE 5038, p. 428). These interactions will introduce an error into the measurement (Smith, Nigel P.; Goelzer, Gary R.; Hanna, Michael; Troccolo, Patrick M., “Minimizing overlay measurement errors”, August 1993, Proceedings of SPIE Volume: 1926 Integrated Circuit Metrology, Inspection, and Process Control VII, Editor(s): Postek, Michael T). The effect can be reduced to some extent by enhancing the resolution of the imaging system, for example by increasing the numerical aperture (NA) of the imaging system. But such an increase would also increase the system aberration and hence the magnitude of tool created measurement errors (particularly TIS) to unacceptable levels. In order to maintain acceptable measurement error levels, some prior art systems use microscopes with NA limited to 0.5. Hence the separation of features in the target must be kept at more than 5 μm if proximity effects in the image are to be ignored. The prior art systems do not correct for these proximity effects.
High speed is one of the key advantages of existing overlay metrology practice. Hence, use of repeated measurements is undesirable, unless they can be made without requiring significantly more time. There remains a need for alternative overlay patterns and/or analysis methods which reduce errors and improve accuracy, and without substantial loss of throughput speed.
In order to achieve the very accurate and precise measurement of overlay required as, design rules shrink to 65 nm and below, all of these issues are considered. While in some cases the prior-art method employing measurement of large targets in the scribe line area may be sufficient for process control in the future, the area of applicability will be process dependent and is most likely to occur in the front end of processes where the device stack, and hence the image formation process, is simpler.